Complementary metal-oxide semiconductor (CMOS) device scaling is facing formidable challenges as scaling moves to the sub-50 nm range. One specific challenge that limits CMOS device performance is series resistance (Rseries). Rseries includes various components, including overlap resistance (Rov), spreading resistance (Rsp, which equals Rext+Rsd) and diffusion contact resistance (Rco). Notably, Rco is proportional to the schottky barrier height (SBH). FIG. 1 illustrates the various components (Rov, Rext, Rsd, Rco) of series resistance in a CMOS device.
Nickel silicide (NiSi) is widely employed in CMOS fabrication for use as the source/drain contact, mainly because of its low resistivity, line width effect, low Si consumption and formation temperature. However, NiSi has a high electron schottky barrier height (SBH) of between about 0.65 and 0.7 eV, which results in high contact resistance.
Because Rco and Rsp account for around 85% or more of the total Rseries in current CMOS devices and further device scaling will increase Rco such that it becomes the dominant component in Rseries, reducing contact resistance is important. Since Rco depends on SBH, reducing SBH will reduce Rseries and improve device performance.
Current techniques for reducing SBH employ impurity segregation at the NiSi/Si interface. An impurity is implanted after source/drain anneal, followed by Ni deposition and NiSi formation. The segregated layer, which could use for example impurities like As, B, N, Cl, S, Se or Al, either passivates the surface or creates interface dipoles to reduce the SBH. The main problems with such a process are that most of the impurity/dopant/metal (1) remains in the bulk of the NiSi material, and (2) may not be fully activated due to the low temperature of silicidation.
For purposes of the following discussion, we shall describe utilization of nitrogen (N) as the impurity, as N is effective in lowering SBH and is a common element used in ion implantation in current CMOS process technology. At low N concentration, surface passivation of dangling bonds help to de-pin the Fermi-level, and therefore lower SBH. While SBH is lowered significantly at high N concentration due to the formation of NiSi2 (nickel disilicide) at the interface, the resistivity Rs (sheet resistance of the material) also increases. The NiSi2 is formed at the interface because N (which is present in large amounts in the bulk silicon) retards Ni diffusion to the NiSi interface. Therefore, achieving high activated impurity concentration at the interface and minimizing excessive formation of NiSi2 are vital in achieving low Rco with good Rs.
The main problem encountered with current SBH engineering techniques is that the peak or large amount of the impurity (e.g., N, Cl, As, B, In) is in the bulk of the NiSi material (i.e., away from the NiSi/Si interface), which is not effective in lowering SBH. Moreover, because there is a need to activate this impurity and the rapid thermal anneal (RTA) temperature needed to achieve NiSi formation may not help achieve high active concentration. When N is used, it retards the diffusion of Ni resulting in a thicker NiSi2 at the interface and increases Rs.
Accordingly, there is a need for an improved fabrication process (and resulting devices) that lower SBH and Rco to improved device performance. Also needed is a new process for more effective SBH engineering that (1) minimizes impurity/dopant/metal diffusion, (2) achieves peak or high impurity/dopant/metal concentration at the silicide-semiconductor interface, (3) achieves high activation of impurity/dopant/metal at the silicide-semiconductor interface, and (4) minimizes the formation of high resistance silicide at the silicide-semiconductor interface.